Fachbereich 6 Mathematik/Informatik

Institut für Informatik


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Publikationen

Zeitschriftenbeiträge   

  • Sang, C. L.; Adams, M.; Hörmann, M.; Hesse, M.; Porrmann, M.; Rückert, U.:
    Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods.

    In: Sensors 2019, 19(3), 616,
    DOI: doi.org/10.3390/s19030616.
  • Cozzi, D.; Korf, S.; Cassano, L.; Hagemeyer, J.; Domenici, A.; Bernardeschi, C.; Sterpone, L.; Porrmann, M.:
    OLT(RE)²: An On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems.

    In: IEEE Transactions on Emerging Topics in Computing, IEEE Computer Society, Vol. 6, No. 4, Oct-Dec 2018, pp. 511-523,
    DOI: dx.doi.org/10.1109/TETC.2016.2586195.
  • Ibraheem, O. W.; Irwansyah, A.; Hagemeyer, J.; Porrmann, M.; Rueckert, U.:
    FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports.
    In: Journal of Signal Processing Systems, June 2018, Springer US,
    DOI: doi.org/10.1007/s11265-018-1381-8.
  • Ax, J.; Sievers, G.; Daberkow, J.; Flasskamp, M.; Vohrmann, M.; Jungeblut, T.; Kelly, W.; Porrmann, M.; Rückert, U.:
    CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data Memories.

    In: IEEE Transactions on Parallel and Distributed Systems, Volume 29, May 2018, pp. 1030-1043,
    DOI: doi.org/10.1109/TPDS.2017.2785799.
  • Oleksiak, A.; Kierzynka, M.; Porrmann, M. et al.:
    M2DC: Modular Microserver DataCentre with Heterogeneous Hardware.

    In: Microprocessors and Microsystems, Volume 52, July 2017, pp. 117-130, Elsevier,
    DOI: doi.org/10.1016/j.micpro.2017.05.019.
  • Irwansyah, A.; Ibraheem, O. W.; Hagemeyer, J.; Porrmann, M.; Rueckert, U.:
    FPGA-based Multi-Robot Tracking.
    In: Journal of Parallel and Distributed Computing, Vol. 107, September 2017, pp. 146-161, Elsevier,
    DOI: dx.doi.org/10.1016/j.jpdc.2017.03.008.
  • Jungeblut, T.; Hübener, B.; Porrmann, M.; Rueckert, U.:
    A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded Processors.

    In: ACM Transactions on Embedded Computing Systems (TECS), Special issue on Application Specific Processors, Vol. 13, No. 2, Article No. 18, September 2013, pp. 1-25.
  • Sterpone, L.; Porrmann, M.; Hagemeyer, J.:
    A Novel Fault Tolerant and Run-Time Reconfigurable Platform for Satellite Payload Processing.
    In: IEEE Transactions on Computers, IEEE Computer Society, Vol. 62, No. 8, August 2013, pp. 1508-1525,
    DOI: doi.ieeecomputersociety.org/10.1109/TC.2013.80.
  • Lachmair, J.; Merényi, E.; Porrmann, M.; Rückert, U.:
    A Reconfigurable Neuroprocessor for Self-Organizing Feature Maps.

    In: Neurocomputing, Vol. 112, July, 2013, pp. 189-199,
    DOI: dx.doi.org/10.1016/j.neucom.2012.11.045.
  • Lütkemeier, S.; Jungeblut, T.; Otnes Berge, H. K.; Aunet, S.; Porrmann, M.; Rückert, U.:
    A 65 nm 32 b Subthreshold Processor with 9T Multi-Vt SRAM and Adaptive Supply Voltage Control.

    In: IEEE Journal of Solid-State Circuits, Vol. 48, No. 1, pp. 8-19, January 2013.
  • Nava, F; Sciuto, D.; Santambrogio, M. D.; Herbrechtsmeier, S.; Porrmann, M.; Witkowski, U.; Rueckert, U.:
    Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms.

    In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Issue 3, pp. 29:1–29:22, August 2011.
  • Koester, M.; Luk, W.; Hagemeyer, J.; Porrmann, M.; Rückert, U.:
    Design Optimizations for Tiled Partially Reconfigurable Systems
    .
    In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19(6), pp. 1048-1061, June, 2011.
  • Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.:
    Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography.

    In: Advances in Radio Science, Vol. 8, pp. 295–305, 2010.
  • Purnaprajna, M.; Porrmann, M.; Rueckert, U.; Hussmann, M.; Thies, M.; Kastens, U.:
    Run-Time Reconfiguration of Multiprocessors Based on Compile-Time Analysis.

    In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 3, Issue 3, Article No.: 17, pp. 1–25, September 2010.
  • Pohl, C.; Paiz, C.; Porrmann, M.:
    vMAGIC – Automatic Code Generation for VHDL.
    In: International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, Volume 2009, Article ID 205149.
  • Purnaprajna, M., Porrmann, M., and Rückert, U.:
    Run-time Reconfigurability in Embedded Multiprocessors.

    In: SIGARCH Computer Architecture News, Volume 37, Number 2, pp. 30–37, July 2009.
  • El-Darawy, M.; Pfau, T.; Hoffmann, S.; Peveling, R.; Wördehoff, C.; Koch, B.; Porrmann, M.; Adamczyk, O.; Noe, R.:
    Fast Adaptive Polarization and PDL Tracking in a Realtime FPGA Based Coherent PolDM-QPSK Receiver.

    In: IEEE Photonics Technology Letters, Volume 20, Issue 21, pp. 1796–1798, November 1, 2008.
  • Hoffmann, S.; Bhandare, S.; Pfau, T.; Adamczyk, O.; Wordehoff, C.; Peveling, R.; Porrmann, M.; Noe, R.:
    Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB Lasers.

    In: IEEE Photonics Technology Letters, Volume 20, Issue 18, pp. 1569–1571, September 15, 2008.
  • Puttmann, C., Shokrollahi, J., Porrmann, M., and Rückert, U.:
    Hardware Accelerators for Elliptic Curve Cryptography.

    In: Advances in Radio Science, Vol. 6, pp. 259–264, 2008.
  • Jungeblut, T., Grünewald, M., Porrmann, M., and Rückert, U.:
    Realtime multiprocessor for mobile ad hoc networks.

    In: Advances in Radio Science, Vol. 6, pp. 239–243, 2008.
  • Pfau, T.; Hoffmann, S.; Adamczyk, O.; Peveling, R.; Herath, V.; Porrmann, M.; Noé, R.:
    Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyond.

    In: Optics Express, Vol. 16, Issue 2, pp. 866–872, January, 2008.
  • Pfau, T.; Peveling, R.; Hauden, J.; Grossard, N.; Porte, H.; Achiam, Y.; Hoffmann, S.; Ibrahim, S.K.; Adamczyk, O.; Bhandare, S.; Sandel, D.; Porrmann, M.; Noe, R.:
    Coherent Digital Polarization Diversity Receiver for Real-Time Polarization-Multiplexed QPSK Transmission at 2.8 Gb/s.

    In: Photonics Technology Letters, IEEE, vol.19, no.24, pp. 1988–1990, Dec.15, 2007.
  • Niemann, J.-C.; Puttmann, C.; Porrmann, M.; Rückert, U.:
    Resource efficiency of the GigaNetIC chip multiprocessor architecture.
    In: Journal of Systems Architecture (JSA), Vol. 53, Issues 5-6, pp. 285-299, May-June 2007.
  • Pfau, T.; Hoffmann, S.; Peveling, R.; Bhandare, S.; Ibrahim, K.; Adamczyk, O.; Porrmann, M.; Noé, R.; Achiam, Y.:
    First Real-Time Data Recovery for Synchronous QPSK Transmission with Standard DFB Lasers.
    In: IEEE Photonics Technology Letters, vol. 18(18), pp. 1907-1909, September 2006.
  • Pfau, T.; Hoffmann, S.; Peveling, R.; Ibrahim, S.; Adamczyk, O.; Porrmann, M.; Bhandare, S.; Noé, R.; Achiam; Y.:
    Synchronous QPSK Transmission at 1.6 Gbit/s with Standard DFB Lasers and Real-time Digital Receiver.

    In: IEE Electronic Letters, Volume 42, Number 20, pp. 1175-1176, September 2006.
  • Kalte, H.; Kettelhoit, B.; Köster, M.; Porrmann, M.; Rückert, U.:
    A System Approach for Partially Reconfigurable Architectures.
    In: International Journal of Embedded Systems (IJES), Inderscience Publisher, Vol. 1, pp. 274-290, 2005.
  • Porrmann, M.; Witkowski, U. Rückert, U.:
    A Massively Parallel Architecture for Self-Organizing Feature Maps.
    In: IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, 14(5): pp. 1110-1121, Sep., 2003.
  • Rüping, S.; Porrmann, M.; Rückert, U.:
    SOM Accelerator System.
    In: Neurocomputing, 21: pp. 31-50, 1998.

Bücher und Buchkapitel   

  • Oleksiak, A.; Kierzynka, M.; Porrmann, M. et al.:
    M2DC – A Novel Heterogeneous Hyperscale Microserver Platform.
    In: Kachris, C., Falsafi, B., Soudris, D. (Eds.), Hardware Accelerators in Data Centers, ISBN 978-3-319-92791-6, Springer, 2018.
  • Sievers, G.; Hübener, B.; Ax, J.; Flasskamp, M.; Kelly, W..; Jungeblut, T.; Porrmann, M.:
    The CoreVA-MPSoC – A Multiprocessor Platform for Software-Defined Radio.

    In: J. Nurmi, J. Isoaho, & F. Garzia (Eds.), Computing Platforms for Software-Defined Radio, Series: Signals and Communication Technology, pp. 29-59, Springer, 2017.
  • Seifried, A.; Trächtler, A.; Kleinjohann, B.; Korf, S.; Porrmann, M. et al.:
    Methods of Improving the Dependability of Self-optimizing Systems.

    In: Gausemeier, J.; Rammig, F.J.; Schäfer, W.; Sextro, W. (Editors) Dependability of Self-Optimizing Mechatronic Systems, pp. 37--171. Springer-Verlag, Heidelberg, Germany, 2014.
  • Dellnitz, M.; Dumitrescu, R.; Flaßkamp, K.; Gausemeier, J.; Hartmann, P.; Iwanek, P.; Korf, S.; Krüger, M.; Ober-Blöbaum, S.; Porrmann, M.; Priesterjahn, C.; Stahl, K., Trächtler, A.; Vaßholz; M.:
    The Paradigm of Self-optimization.

    In: Gausemeier, J.; Rammig, F.J.; Schäfer, W. (Editors) Design Methodology for Intelligent Technical Systems – Develop Intelligent Technical Systems of the Future, pp. 1-25. Springer-Verlag, Heidelberg, Germany, 2014.
  • Gausemeier, J.; Korf, S.; Porrmann, M.; Stahl, K.; Sudmann, O.; Vaßholz, M.:
    Development of Self-Optimizing Systems.
    In: Gausemeier, J.; Rammig, F.J.; Schäfer, W. (Editors) Design Methodology for Intelligent Technical Systems – Develop Intelligent Technical Systems of the Future, pp. 65-117. Springer-Verlag, Heidelberg, Germany, 2014.
  • Jungeblut, T.; Liß, C.; Porrmann, M.; Rückert, U.:
    Design-space Exploration for Flexible WLAN Hardware.
    In: Zorba, N.; Skianis, C.; Verikoukis, C. (Editors) Cross Layer Designs in WLAN Systems, ISBN: 978-1848768109, Troubador Publishing, Leicester, UK, pp. 521-564, November 2011.
  • Adelt, P.; Donoth, J.; Gausemeier, J.; Geisler, J.; Henkler, S.; Kahl, S.; Klöpper, B.; Krupp, A.; Münch, E.; Oberthür, S.; Paiz, C.; Podlogar, H.; Porrmann, M.; Radkowski, R.; Romaus, C.; Schmidt, A.; Schulz, B.; Vöcking, H.; Witkowski, U.; Witting, K.; Znamenshchykov, O.:
    Selbstoptimierende Systeme des Maschinenbaus – Definitionen, Anwendungen, Konzepte.
    HNI-Verlagsschriftenreihe, 2008, Band 234.
  • Paiz, C.; Pohl, C.; Porrmann, M.:
    Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design.
    In: Juan Andrade-Cetto, Jean-Louis Ferrier, Jos´e Miguel Costa dias Pereira, Joaquim Filipe (Editors) Informatics in Control, Automation and Robotics, Vol. 3, pp. 355-372, Springer-Verlag, 2008.
  • Koester, M.; Kalte, H.; Porrmann, M.; Rückert, U.:
    Defragmentation Algorithms for Partially Reconfigurable Hardware.
    In: VLSI-SoC: From Systems to Silicon. IFIP International Federation for Information Processing, Vol. 240, pp. 41-53, Springer, Boston, USA, 2007.
  • Porrmann, M.; Witkowski, U.; Rückert, U.:
    Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware.
    In: Omondi, Amos; Rajapakse, Jagath (Editors) FPGA Implementations of Neural Networks Springer-Verlag, Chapter 9, pp. 247-269, 2006.
  • Grünewald, M.; Niemann, J.; Porrmann, M.; Rückert, U.:
    A framework for design space exploration of resource efficient network processing on multiprocessor SoCs.
    In: Crowely, Patrick; Franklin, Mark A.; Hadimioglu, Haldun; Onufryk, Peter Z. (Editors) Network Processor Design: Issues and Practices Morgan Kaufmann Publishers, vol.3, Chapter 12, pp. 245-277, 2005.
  • Porrmann, M.:
    Leistungsbewertung eingebetteter Neurocomputersysteme.
    Dissertation, Universität Paderborn, Heinz Nixdorf Institut, Schaltungstechnik, HNI-Verlagsschriftenreihe, Paderborn, Band 104, 2002.

Patente       

  • DE10 2010 021 825 A1
    Christmann, W.; Strugholtz, M.; Hagemeyer, J.; Porrmann. M.:
    Mehrprozessor-Computersystem mit einer Mehrzahl von Arbeitsprozessoren und einer Mehrzahl von Überwachungsprozessoren zur Überwachung der Arbeitsprozessoren. (Zum Patent angemeldet.)
  • DE10 2006 008 466 B4 2011.07.21
    Niemann, J.-C.; Sauer, C.; Porrmann, M.; Rueckert, U.:
    Flexible Beschleunigungseinheit für die Verarbeitung von Datenpaketen.

Konferenzbeiträge   

2018
  • Sang, C. L.; Adams, M.; Hörmann, M.; Hesse, M.; Porrmann, M.; Rückert, U.:
    An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods.
    In: 9th International Conference on Indoor Positioning and Indoor Navigation (IPIN 2018), Nantes, France, September 24-27, 2018.
  • Cristal, A.; Unsal, O. S.; …; Porrmann, M. et al.:
    LEGaTO: First Steps Towards Energy-Efficient Toolset for Heterogeneous Computing (Invited paper).
    In: International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS XVIII, Samos Island, Greece, July 15-19, 2018.
  • Klimeck, D.; Meyer, H. G.; Hagemeyer, J.; Porrmann, M.; Rückert, U.:
    Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications.
    In: 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2018), Milan, Italy, July 10-12, 2018, pp. 89-92.
  • Klarhorst, C.; Flasskamp, M.; Ax, J.; Jungeblut, T.; Kelly, W.; Porrmann, M.; Rueckert, U.:
    Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems.
    In: 6th International Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES 2018), Manchester, UK, January 22, 2018.
2017
  • Ibraheem, O. W.; Irwansyah, A.; Hagemeyer, J.; Porrmann, M.; Rueckert, U.:
    Reconfigurable Vision Processing System for Player Tracking in Indoor Sports.
    In: Conference on Design and Architectures for Signal and Image Processing (DASIP 2017), Dresden, Germany, September 27-29, 2017.
  • Ax, J.; Kucza, N.; Vohrmann, M.; Jungeblut, T.; Porrmann, M.; Rueckert, U.:
    Comparing synchronous, mesochronous and asynchronous NoCs for GALS based MPSoCs.
    In: IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Seoul, South Korea,  September 18-20, 2017.
  • Lachmair, J.; Mieth, T.; Griessl, R.; Hagemeyer, J.; Porrmann, M.:
    From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining.
    In: International Joint Conference on Neural Networks (IJCNN 2017), pp. 4299-4308, Anchorage, Alaska, USA, May 14 - 19, 2017.
  • Oleksiak, A.; Kierzynka, M.; …; Porrmann, M. et al.:
    M2DC: Modular Microserver Datacentre with Heterogeneous Hardware.
    In: Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017), co-located with HiPEAC 2017, Stockholm, Sweden, January 23, 2017.
2016
  • Oleksiak, A.; Kierzynka, M.; …; Porrmann, M. et al.:
    The M2DC Project: Modular Microserver DataCentre (Invited paper).
    In: 19th Euromicro Conference on Digital Systems Design, Limassol, Cyprus, August 31 - September 2, 2016.
  • Oleksiak, A.; Kierzynka, M.; …; Porrmann, M. et al.:
    Data Centres for IoT Applications: the M2DC Approach (Invited paper).
    In: International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS XVI, Samos Island, Greece, July 18-21, 2016.
  • Flasskamp, M.; Sievers, G.; Ax. J.; Klarhorst, C.; Jungeblut, T.; Kelly, W.; Thies, M.; Porrmann, M.:
    Performance Estimation of Streaming Applications for Hierarchical MPSoCs.
    In: Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO). ACM Press, Prague, Czech Republic, January 18, 2016.
2015
  • Ibraheem, O. W.; Irwansyah, A.; Hagemeyer, J.; Porrmann, M.; Rückert. U.:
    A Resource-Efficient Multi-Camera GigE Vision IP Core for Embedded Vision Processing Platforms.
    In: 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Mayan Riviera, Mexico, December 7-9, 2015.
  • Irwansyah, A.; Ibraheem, O. W.; Hagemeyer, J.; Porrmann, M.; Rückert. U.:
    FPGA-based Circular Hough Transform with Graph Clustering for Vision-based Multi-Robot Tracking.
    In: 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Mayan Riviera, Mexico, December 7-9, 2015.
  • Griessl, R.; Peykanu, M.; Hagemeyer, J.; Porrmann, M.; Krupop, S.; vor dem Berge, M.; Kosmann, L.; Knocke, P.; Kierzynka, M.; Oleksiak, A.:
    FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters.
    In: First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputig 2015, Austin, TX, USA, November 15, 2015.
  • Ax, J.; Sievers, G.; Flasskamp, M.; Kelly, W.; Jungeblut, T.; Porrmann, M.:
    System-Level Analysis of Network Interfaces for Hierarchical MPSoCs.
    In: 8th International Workshop on Network on Chip Architectures (NoCArc-15), Waikiki, Hawaii, December 6th, 2015.
  • Sievers, G.; Daberkow, J.; Ax, J.; Flasskamp, M.; Kelly, W.; Jungeblut, T.; Porrmann, M.; Rückert, U.:
    Comparison of shared and private L1 data memories for an embedded MPSoC in 28nm FD-SOI.
    In: 9th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-15), Turin, Italy, September 23-25, 2015, pp. 175-181.
  • Vohrmann, M.; Chatterjee, S.; Lütkemeier, S.; Jungeblut, T.; Porrmann, M.; Rückert, U.:
    A 65 nm Standard Cell Library for Ultra Low-power Applications.
    In: 22nd European Conference on Circuit Theory and Design, ECCTD2015, Trondheim, Norway, August 24-26, 2015.
  • Buda, A.; Walter, M.; Hartfiel, J.; Ax, J.; Nußbaum, C.; Jungeblut, T.; Porrmann, M.:
    Automatische Protokollanpassung von Echtzeit-Ethernet-Standards durch FPGA-Technologien.
    In: AUTOMATION 2015, Baden-Baden, Germany, June 11-12, 2015, pp. 1011-1022.
  • Sievers, G.; Ax, J.; Kucza, N.; Flaßkamp, M.; Jungeblut, T.; Kelly, W.; Porrmann, M.; Rückert, U.:
    Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI.
    In: 2015 IEEE Int'l Symposium on Circuits & Systems (ISCAS), Lisbon, Portugal, May 24-27, 2015, pp. 1925-1928.
  • Herbrechtsmeier, S.; Jungeblut, T.; Porrmann, M.; Rückert, U.:
    Datenflussmodellierung als Methode zur Optimierung von Entwicklungsprozessen am Beispiel der Leiterplattenentwicklung.
    In: Wissenschaftsforum Intelligente Technische Systeme, 10. Paderborner Workshop Entwurf mechatronischer Systeme, pp. 265-276, April 23-24, 2015, Paderborn, Germany.
2014
  • Irwansyah, A.; Ibraheem, O.; Klimeck, D.; Porrmann, M.; Rückert, U.:
    FPGA-based Generic Architecture for Rapid Prototyping of Video Hardware Accelerators using NoC AXI4-Stream Interconnect and GigE Vision Camera Interfaces.

    In: Bildverarbeitung in der Automation (BVAu) 2014, Lemgo, Germany, November 19, 2014.
  • Walter, M.; Ax, J.; Buda, A.; Nußbaum, K.; Hartfiel, J.; Jungeblut, T.; Porrmann, M.:
    Dynamische Rekonfiguration von Echtzeit-Ethernet-Standards mit harten Echtzeit-anforderungen.
    In: Kommunikation in der Automation – KommA 2014, Lemgo, Germany, November 18, 2014.
  • Sorrenti,D.; Cozzi, D.; Korf, S.; Cassano, L.; Hagemeyer, J.; Porrmann, M.; Bernardeschi, C.:
    Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems.
    In: 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. Amsterdam, The Netherlands, October 1-3, 2014.
  • Cozzi, D.; Jungewelter, D.; Kleibrik, D.; Korf, S.; Hagemeyer, J.; Porrmann, M.; Ilstad, J.:
    AXI-based SpaceFibre IP CORE Implementation.
    In: SpaceWire 2014 – 6th International SpaceWire Conference, Athens, Greece, September 22-26, 2014, pp.196-201.
  • Hübener, B.; Sievers, G.; Jungeblut, T.; Porrmann, M.; Rückert, U.: CoreVA:
    A Configurable Resource-efficient VLIW Processor Architecture.
    In: 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, Milan, Italy, August 26-28, 2014, pp. 9-16.
  • Griessl, R.; Peykanu, M.; Hagemeyer, J.; Porrmann, M.; Krupop, S.; vor dem Berge, M.; Kiesel, T.; Christmann, W.:
    A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters.
    In: 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, Milan, Italy, August 26-28, 2014, pp. 146-153.
  • Cassano, L.; Cozzi, D.; Jungewelter, D.; Korf, S.; Hagemeyer, J.; Porrmann, M.; Bernardeschi, C.:
    An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems.
    In: 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2014, Santorini, Greece, May 6-8, 2014, pp. 133-138
  • Sabena, D.; Sterpone, L.; Schölzel, M.; Koal, T.; Vierhaus, H. T.; Wong, S.; Glein, R.; Rittner, F.; Stender, C.; Porrmann, M.; Hagemeyer, J.:
    Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications?
    In: IEEE Proceedings of 19th IEEE European Test Symposium, Paderborn, Germany, May 26-30, 2014, pp. 175-182.
2013
  • Sievers, G.; Christ, P.; Einhaus, J.; Jungeblut, T.; Porrmann, M.; Rückert, U.:
    Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications.
    In: Norchip 2013, November 11-12, Vilnius, Lithuania.
  • Christ, P.; Sievers, G.; Einhaus, J.; Jungeblut, T.; Porrmann, M.; Rückert, U.:
    Pareto-Optimal Signal Processing on Low-Power Microprocessors.
    In: IEEE Sensors 2013, November 3-6, Baltimore, Maryland, USA, pp. 1-4,
    DOI: 10.1109/ICSENS.2013.6688593.
  • Desogus, M.; Sterpone, L.; Porrmann, M.; Hagemeyer, J.; Ilstad, J.:
    Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience.
    In: RADECS 2013, Oxford, UK, September 23-27, 2013, pp. 13-16.
  • Sterpone, L.; Sabena, D.; Ullah, A.; Porrmann, M.; Hagemeyer, J.; Ilstad, J.:
    Dynamic Neutron Testing of Dynamically Reconfigurable Processing Modules Architecture.
    In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), June 24-27, 2013, Torino, Italy.
  • Korf, S.; Sievers, G.; Ax, J.; Cozzi, D.; Jungeblut, T.; Hagemeyer, J.; Porrmann, M.; Rückert, U.:
    Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme.
    In: Wissenschaftsforum Intelligente Technische Systeme, 9. Paderborner Workshop Entwurf mechatronischer Systeme, April 18-19, 2013, Paderborn, Germany, pp. 79-90.
  • Cassano, L.; Cozzi, D.; Korf, S.; Hagemeyer, J.; Porrmann, M.; Sterpone, L.:
    On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems.
    In: Proceedings of DATE: Design, Automation and Test in Europe, Grenoble, France, March 18-22, 2013, pp. 717-720.
2012
  • Luetkemeier, S.; Porrmann, M.; Jungeblut, T.; Rueckert, U.:
    A 200 mV 32-bit Subthreshold Processor with Adaptive Supply Voltage Control.
    In: Proceedings of the 2012 IEEE International Solid-State Circuits Conference (ISSCC), February 19-23, 2012, pp. 484-485, San Francisco, CA.
  • Lachmair, J.; Merenyi, E.; Porrmann, M.; Rueckert, U.:
    gNBXe – a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps.
    In: European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2012, April 25-27, 2012, Bruges, Belgium.
  • Jungeblut, T.; Ax, J.; Porrmann, M.; Rückert, U.:
    A TCMS-based architecture for GALS NoCs.
    In: 2012 IEEE International Symposium on Circuits and Systems, May 20-23, 2012, pp. 2721-2724, Seoul, Korea.
  • Durelli, G.; Santambrogio, M.D.; Cresci, F.; Porrmann, M.; Sciuto, D.:
    Mini-Robot’s Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.

    In: 19th Reconfigurable Architectures Workshop, RAW 2012, May 21-22, 2012, pp. 437-442, Shanghai, China.
  • Porrmann, M.:
    Adaptive hardware platforms for self-optimizing mechatronic systems.
    In: International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-oriented Environments, DAC – Design Automation Conference 2012, June 3, 2012, San Francisco, CA, USA.
  • Hagemeyer, J.;  Hilgenstein, A.; Jungewelter, D.; Cozzi, D.; Rueckert, U.; Korf, S.; Porrmann, M. et al.:
    A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing.
    In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012), June 25-28, 2012, pp. 9-16, Erlangen, Germany.
  • Romoth, J.; Jungewelter, D.; Hagemeyer, J.; Porrmann, M.; Rueckert, U.:
    Optimizing Inter-FPGA Communication by Automatic Cannel Adaptation.
    In: ReConFig 2012: International Conference on Reconfigurable Computing and FPGAs, pp.1-7, Dec. 5-7, 2012, Cancun, Mexico.
2011
  • Korf, S., Cozzi, D., Koester, M., Hagemeyer, J., Porrmann, M., Santambrogio, M. D., Rueckert, U.:
    Automatic HDL-based generation of homogeneous hard macros for FPGAs.
    In: Proceedings of The 19th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Salt Lake City, UT, USA, May 1-3, pp. 125-132, 2011.
  • Jungeblut, T.; Ax, J.; Sievers, G.; Hübener, B.; Porrmann, M.; Rückert, U.:
    Resource Efficiency of Scalable Processor Architectures for SDR-based Applications.
    In: RADCOM 2011 – Radar, Communication and Measurement, Hamburg, Germany, April 6-7, 2011.
  • Sterpone, L.; Margaglia, F.; Koester, M.; Hagemeyer, J.; Porrmann, M.:
    Analysis of SEU Effects in Partially Reconfigurable SoPCs.
    In: Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), pp.129-136, San Diego, CA, USA, June 6-9, 2011.
  • Grawinkel, M.; Schafer, T.; Brinkmann, A.; Hagemeyer, J.; Porrmann, M.:
    Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.
    In: MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp.297–306, Singapore, July 25-27, 2011.
2010
  • Jungeblut, T.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.:
    A Framework for the Design Space Exploration of Software-Defined Radio Applications.
    In: Chatzimisios, P.; Verikoukis, C.; Santamaría, I.; Laddomada, M.; Hoffmann, O. (Ed.): Mobile Lightweight Wireless Systems, Lecture Notes of the Inst. for Computer Sciences, Social Inform. and Telecom. Engineering, Vol. 45, 2010, Springer Berlin Heidelberg, pp 148-159.
  • Puttmann, C.; Porrmann, M.; Grassi, P. R.; Santambrogio, M.; Rückert, U.:
    High Level Specification of Embedded Listeners for Monitoring of Network-on-Chips.
    In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pp. 3333-3336, May 30 - June 2, 2010.
  • Puttmann, Christoph; Porrmann, Mario; Rückert, Ulrich:
    Extending GigaNoC towards a Dependable Network-on-Chip.
    In: Digest of the DAC Workshop on Diagnostic Services in Network-on-Chips (DSNOC), Anaheim, CA, USA, June 13, 2010.
  • Dittmann, F.; Linke, M.; Hagemeyer, J.; Koester, M.; Lallet, J.; Pohl, C.; Porrmann, M.; Harris, J.; Ilstad, J.:
    Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks.
    In: Proceedings of the International SpaceWire Conference 2010, pp. 193-196, St. Petersburg, Russia, June 22-24 2010.
  • Jungeblut, T.; Sievers, G.; Porrmann, M.; Rückert, U.:
    Design Space Exploration for Memory Subsystems of VLIW Architectures.
    In: Proceedings of the fifth IEEE International Conference on Networking, Architecture, and Storage (NAS2010), pp. 377-385, Macau, China, July 15-17, 2010.
  • Porrmann, M.; Hagemeyer, J.; Pohl, C.; Romoth, J.; Strugholtz, M.:
    RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing.
    In: Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing, Volume 19, pp. 592–599, ISBN: 978-1-60750-529-7, IOS press, 2010.
2009
  • Herath, V.; Peveling, R.; Pfau, T.; Adamczyk, O.; Hoffmann, S.; Wördehoff, C.; Porrmann, M.; Noé, R.:
    Chipset for a Coherent Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of OFC/NFOEC 2009, San Diego, California, USA, March 22-26, 2009.
  • Pfau, T.; Peveling, R.; Herath, V.; Hoffmann, S.; Wördehoff, C.; Adamczyk, O.; Porrmann, M.; Noé, R.:
    Towards Real-Time Implementation of Coherent Optical Communication.
    In: Proceedings of OFC/NFOEC 2009, San Diego, California, USA, March 22-26, 2009, invited paper.
  • Köster, M.; Luk, W.; Hagemeyer, J.; Porrmann, M.:
    Design Optimizations to Improve Placeability of Partial Reconfiguration Modules.
    In: Proceedings of DATE: Design, Automation and Test in Europe, Nice, France, April 20-24, 2009.
  • Grassi, P. R.; Santambrogio, M. D.; Puttmann, C.; Pohl, C.; Porrmann, M.:
    A High Level Methodology for Monitoring Network-on-Chips.
    In: Diagnostic Services in Network-on-Chips (DSNOC’09), Workshop at Design, Automation and Test in Europe DATE, Nice, France, April 24, 2009.
  • Porrmann, M.; Hagemeyer, J.; Romoth, J.; Strugholtz, M.:
    Rapid Prototyping of Next-Generation Multiprocessor SoCs.
    In: Proceedings of Semiconductor Conference Dresden, SCD 2009, Dresden, Germany, April 29-30, 2009, invited paper.
  • Liß, C.; Porrmann, M.; Rückert, U.:
    Early Exploration of Network Processor Architectures Using Cadence InCyte Chip Estimator.
    In: CDNLive, EMEA2009, Munich, Germany, May 18-20, 2009 (best paper award).
  • Jungeblut, T.; Klassen, D.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.:
    Design Space Exploration for Next Generation Wireless Technologies.
    In: Electrical and Electronic Engineering for Communication (EEEfCOM) 2009, Ulm, Germany, June 24-25, 2009, Invited talk.
  • Porrmann, M.; Purnaprajna, M.: Puttmann, C.:
    Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance.
    In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009), San Francisco, California, USA, pp. 467--473, July 29 – August 1, 2009, invited paper.
  • Grassi, P. R.; Santambrogio, M. D.; Hagemeyer, J.; Pohl, C.; Porrmann, M.: SiLLis:
    A Simplified Language for Monitoring and Debugging of Reconfigurable Systems.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09), Las Vegas, USA, July 13-16, pp. 174–180, 2009.
  • Purnaprajna, M.; Pohl, C.; Porrmann, M.; Rückert, U.:
    Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09), Las Vegas, USA, July 13-16, pp. 119–125, 2009.
  • Dreesen, R.; Jungeblut, T.; Thies, M.; Porrmann, M.; Rückert, U.; Kastens, U.:
    A Synchronization Method for Register Traces of Pipelined Processors.
    In: Proceedings of the International Embedded Systems Symposium 2009 (IESS '09), Schloss Langenargen, Germany, September 14-16, pp. 207–217, 2009.
  • Paiz, C.; Hagemeyer, J.; Pohl, C.; Porrmann, M.; Rückert, U.; Schulz, B.; Peters, W.; Böcker, J.:
    FPGA-Based Realization of Self-Optimizing Drive-Controllers.
    In: Proceedings of the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009), pp. 2868–2873, Porto, Portugal, November 3-5, 2009.
  • Paiz, C.; Pohl, C.; Radkowski, R.; Hagemeyer, J.; Porrmann, M.:
    FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications.
    In: Proc. of the 2009 Int. Conf. on Field-Programmable Technology (FPT'09), pp. 372–375, Sydney, Australia, December 9-11, 2009.
  • Pohl, C.; Hagemeyer, J.; Romoth, J.; Porrmann, M.; Rückert, U.:
    Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks.
    In: Proc. of the 2009 Int. Conf. on Field-Programmable Technology (FPT'09), pp. 368–371, Sydney, Australia, December 9-11, 2009.
2008
  • Hagemeyer, J.; Köster, M.; Porrmann, M.:
    Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures.
    In: 1. GI/ITG KuVS Fachgespräch Virtualisierung, Paderborn, Germany, pp. 19–28, February 11–12, 2008.
  • Münch, E.; Gambuzza, A.; Paiz, C.; Pohl, C.; Porrmann, M.:
    FPGA-in-the-Loop Simulations with CAMEL-View.
    In: Self-optimizing Mechatronic Systems: Design the Future, 7th International Heinz Nixdorf Symposium, Paderborn, Germany, pp. 429–445, February 20-21, 2008.
  • Pfau, T.; Wördehoff, C.; Peveling, R.; Ibrahim, S. K.; Hoffmann, S.; Adamczyk, O.; Bhandare, S.; Porrmann, M.; Noé, R.; Koslovsky, A.; Achiam, Y.; Schlieder, D.; Grossard, N.; Hauden, J.; Porte, H.:
    Ultra-Fast Adaptive Digital Polarization Control in a Realtime Coherent Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of OFC/NFOEC 2008, San Diego, California, USA, February 24-28, 2008.
  • Purnaprajna, M.; Puttmann, C.; Porrmann, M.:
    Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography.
    In: Proceedings of DATE: Design, Automation and Test in Europe, Munich, Germany, pp. 1462–1467, March 10-14, 2008.
  • Puttmann, C.; Shokrollahi, J.; Porrmann, M.:
    Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography.
    In: Proceedings of the 5th International Conference on Information Technology: New Generations, ITNG 2008, Las Vegas, Nevada, USA, pp. 131-136, April 7-9, 2008.
  • Griese, B.; Brinkmann, A.; Porrmann, M.:
    SelfS – A Real-Time Protocol for Virtual Ring Topologies.
    In: Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS'08), (on CD), Miami, Florida, USA, April 14, 2008.
  • Purnaprajna, M.; Porrmann, M.:
    Run-time Reconfigurable Multiprocessors.
    In: Proceedings of the 22nd International Parallel and Distributed Processing Symposium (IPDPS 2008), PhD Forum, Miami, Florida, USA, April, 2008.
  • Pohl, C.; Paiz, C.; Porrmann, M.:
    vMAGIC – VHDL Manipulation and Automation for Reliable System Development.
    In: 3rd International Workshop on Reconfigurable Computing Education, (on CD), April 10, 2008, Montpellier, France.
  • Hoffmann, S.; Pfau, T.; Adamczyk, O.; Wördehoff, C.; Peveling, R.; Porrmann, M.; Noé, R.; Bhandare, S.:
    Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB Lasers.
    In: Proc. OSA Topical Meeting Coherent Optical Technologies and Applications (COTA), July 13-16, 2008, CWB4, Boston, MA, USA.
  • Pfau, T.; El-Darawy, M.; Wördehoff, C.; Peveling, R.; Hoffmann, S.; Koch, B.; Adamczyk, O.; Porrmann, M.; Noé, R.:
    32-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of the 2008 IEEE/LEOS Summer Topical Meetings, Acapulco, Mexico, pp. 105–106, July 21–23.
  • Noé, R.; Hoffmann, S.; Pfau, T.; Adamczyk, O.; Herath, V.; Peveling, R.; Porrmann, M.:
    Realtime Digital Polarization and Carrier Recovery in a Polarization-Multiplexed Optical QPSK Transmission.
    In: Proc. IEEE/LEOS Summer Topical Meetings 2008, pp. 99–100, July 21-23, 2008, Acapulco, Mexico, (invited paper).
  • El-Darawy, M.; Pfau, T.; Wördehoff, C.; Koch, B.; Hoffmann, S.; Peveling, R.; Porrmann, M.; Noé, R.:
    Realtime 40 krad/s Polarization Tracking with 6 dB PDL in Digital Synchronous Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of ECOC 2008, Brussels, Belgium, September 21-25, 2008.
  • Purnaprajna, M.; Porrmann, M.:
    Run-time Reconfigurable Cluster of Processors.
    In: Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society, November 8-12, 2008, Lake Como, Italy.
2007
  • Niemann, J.-C.; Liss, C.; Porrmann, M.; Rückert, U.:
    A multiprocessor cache for massively parallel SoC architectures.
    In: Proceedings of ARCS'07: Architecture of Computing Systems, pp. 83-97, Zurich, Switzerland, March 12-15, 2007.
  • Pohl, C.; Paiz, C.; Porrmann, M.:
    Hardware-in-the-Loop Entwicklungsumgebung für informationsverarbeitende Komponenten mechatronischer Systeme.

    In: 5. Paderborner Workshop Entwurf mechatronischer Systeme, pp. 69-79, March 22-23, 2007.
  • Rana, V.; Santambrogio, M.; Sciuto, D.; Kettelhoit, B.; Koester, M; Porrmann, M.; Rückert, U.:
    Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.
    In: Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS 2007) – Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, Long Beach, California, USA, March 26 - 27, (on CD) 2007.
  • Paiz, C.; Kettelhoit, B.; Porrmann, M.:
    A design framework for FPGA-based dynamically reconfigurable digital controllers.
    In: Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS2007, pp. 3708-3711, New Orleans, USA, May 27-30, 2007.
  • Paiz, C.; Porrmann M.:
    The Utilization of Reconfigurable Hardware to Implement Digital Controllers: A Review.
    In: Proceedings of the IEEE International Symposium on Industrial Electronics, pp. 2380-2385, Vigo, Spain, June 4-7, 2007.
  • Noe, R.; Pfau, T.; Adamczyk, O.; Peveling, R.; Herath, V.; Hoffmann, S.; Porrmann, M.; Ibrahim, S. K.; Bhandare, S.:
    Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission.
    In: Proceedings of System Microwave Symposium, 2007. IEEE/MTT-S International, Honolulu, HI, USA, pp. 1503 – 1506, June 3-8, 2007 (invited paper).
  • Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.:
    Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '07), Las Vegas, USA, June 25-28, 2007 (Distinguished Paper).
  • Pfau, T.; Peveling, R.; Hoffmann, S.; Bhandare, S.; Ibrahim, S.; Sandel, D.; Adamczyk, O.; Porrmann, M.; Noé, R.; Achiam, Y.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Hauden, J.; Grossard, N.; Porte, H.:
    PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity Receiver.
    In: Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, pp. 17-18, Portland, USA, July 23-25, 2007.
  • Pfau, T.; Adamczyk, O.; Herath, V.; Peveling, R.; Hoffmann, S.; Porrmann, M.; Noe, R.:
    Realtime Optical Synchronous QPSK Transmission with DFB lasers.
    In: Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, pp. 15-16, Portland, USA, July 23-25, 2007.
  • Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.:
    A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs.
    In: Proceedings of the 17th International Conference on Field Programmable Logic and its Applications (FPL 2007), pp. 331-338, Amsterdam, Netherlands, August 27-29, 2007.
  • Puttmann, C.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
    GigaNoC – A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors.
    In: Proceedings of the 10th EUROMICRO Conference on Digital System Design, pp. 495-502, Luebeck, Germany, August 27-31, 2007.
  • Schulz, B.; Paiz, C.; Hagemeyer, J.; Mathapati, S.; Porrmann, M.; Böcker, J.:
    Run-Time Reconfiguration of FPGA-Based Drive Controllers.
    In: Proceedings of the 12th European Conference on Power Electronics and Applications, (on CD), Aalborg, Denmark, September 2-5, 2007.
  • Pfau, T.; Peveling, R.; Samson, F.; Romoth, J.; Hoffmann, S.; Bhandare, S.; Ibrahim, S.; Sandel, D.; Adamczyk, O.; Porrmann, M.; Noé, R.; Hauden, J.; Grossard, N.; Porte, H.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Achiam, Y.:
    Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization Tracking.
    In: Proceedings of ECOC 2007, Vol.3, pp.263-264, Berlin, September 16-20, 2007.
  • Hußmann, M.; Thies, M.; Kastens, U.; Purnaprajna, M.; Porrmann, M; Rückert, U.:
    Compiler-Driven Reconfiguration of Multiprocessors.
    In: Proceedings of Workshop on Application Specific Processors (WASP), held in conjunction with CODES+ISSS, pp. 3-10, Salzburg, Austria, October 4, 2007.
2006
  • Porrmann, M.; Niemann, J.-C.:
    Teaching Reconfigurable Computing – Theory and Practice.
    In: 1st International Workshop on Reconfigurable Computing Education, on CD, Karlsruhe, Germany, March 1, 2006.
  • Sauer, C.; Gries, M.; Dirk, S.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
    A Lightweight NoC for the NOVA Packet Processing Platform.
    In: Design, Automation and Test in Europe DATE, Future Interconnect and Network-on-Chip (NoC) Workshop, on CD, Munich, Germany, March 6-10, 2006.
  • Niemann, J.-C.; Puttmann, C.; Porrmann, M.; Rückert, U.:
    GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.
    In: ARCS'06 Architecture of Computing Systems, pp. 268-282, March13-16, 2006 (best paper award).
  • Hagemeyer, J.; Kettelhoit, B.; Porrmann, M.:
    Dedicated Module Access in Dynamically Reconfigurable Systems.

    In: Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium, on CD, Rhodes Island, Greece, April 25-29, 2006.
  • Kalte, H.; Porrmann, M.:
    REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs.
    In: Proceedings of the 3rd Conference on Computing Frontiers, pp. 403-412, Ischia, Italy, May 03 - 05, 2006.
  • Jäger, B.; Porrmann, M.; Rückert, U.:
    Bio-Inspired Massively Parallel Architectures for Nanotechnologies.
    In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006), pp. 1961 – 1964, Island of Kos, Greece, May 21 – 24, 2006.
  • Hoffmann, S.; Pfau, T.; Adamczyk, O.; Peveling, R.; Porrmann, M.; Noé, R.:
    Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver Concept.
    In: Coherent Optical Technologies and Applications (COTA 2006), on CD, OSA, Whistler, BC, Canada, June 28-30, 2006.
  • Koester, M.; Kalte H.; Porrmann M.:
    Relocation and Defragmentation for Heterogeneous Reconfigurable Systems.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '06), CSREA Press, pp. 70-76, Las Vegas, USA, June 27-30, 2006.
  • Hoffmann, S.; Pfau, T.; Peveling, R.; Bhandare, S.; Adamczyk, O.; Porrmann M.; Noé, R.:
    Synchrone 1,6-Gbit/s-QPSK-Datenübertragung in Echtzeit mit DFB-Lasern.
    In: Workshop der ITG Fachgruppe 5.3.1, Modellierung photonischer Komponenten und Systeme, pp. 21-27, Nürnberg, Germany, July 17-18, 2006.
  • Griese, B.; Porrmann, M.:
    A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems.
    In: Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006), pp. 115-124, Santiago de Chile, Chile, August 20-25, 2006.
  • Kettelhoit, B.; Porrmann, M.:
    A Layer Model for Systematically Designing Dynamically Reconfigurable Systems.
    In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications, pp. 547-552, Madrid, Spain, August, 28-30, 2006.
  • Paiz, C.; Pohl, C.; Porrmann, M.:
    Reconfigurable Hardware in-the-Loop Simulations for Digital Control Design.
    In: 3rd International Conference on Informatics in Control, Automation and Robotics (ICINCO), pp. 39-46, Setubal, Portugal, August 2006.
  • Griese, B.; Kettelhoit, B.; Porrmann, M.:
    Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors.
    In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, pp.214-219, Bialystok, Poland, September 13-17, 2006.
  • Sauer, C.; Gries, M.; Niemann, J.; Porrmann, M.; Thies, M.:
    Application-driven Development of Concurrent Packet Processing Platforms.
    In: 5th International Symposium on Parallel Computing in Electrical Engineering, pp.55-61, Bialystok, Poland, September 13-17, 2006.
  • Pfau, T.; Hoffmann, S.; Peveling, R.; Bhandare, S.; Adamczyk, O.; Porrmann, M.; Noé, R.; Achiam, Y.:
    1.6 Gbit/s Real-Time Synchronous QPSK Transmission with Standard DFB Lasers.
    In: Proc. 32nd European Conference on Optical Communication (ECOC 2006), Cannes, France, September 24-28, 2006.
  • Paiz, C.; Chinapirom, T.; Witkowski U.; Porrmann, M.:
    Dynamically Reconfigurable Hardware for Autonomous Mini-Robots.
    In: 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON-2006), pp. 3981-3986, Paris, France, November 2006.
2005
  • Kettelhoit, B.; Kalte, H.; Porrmann, M.; Rückert, U.:
    Dynamically Reconfigurable Hardware for Self-Optimizing Mechatronic Systems.

    In: 5. GMM/ITG/GI-Workshop  Multi-Nature Systems, pp. 97-101, Dresden, Germany, February 2005.
  • Kettelhoit, B.; Klassen, A.; Paiz, C.; Porrmann, M.; Rückert, U.:
    Rekonfigurierbare Hardware zur Regelung mechatronischer Systeme.

    In: 3. Paderborner Workshop: Intelligente mechatronische Systeme, pp. 195-205, Paderborn, Germany, March 30-31, 2005.
  • Köster, M.; Porrmann, M.; Rückert, U.:
    Placement-Oriented Modeling of Partially Reconfigurable Architectures.

    In: Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) – Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD, Denver, Colorado, USA, April 4 – 5, 2005.
  • Kalte, H.; Gareth, L.; Porrmann, M.; Rückert, U.:
    REPLICA: A bitstream manipulator filter for module relocation in partial reconfigurable systems.

    In: Proceedings of the 19th International Parallel and Distributed Processing Symposium, Reconfigurable Architectures Workshop, IEEE Computer Society, on CD, Denver, Colorado, USA, April 4 – 5, 2005.
  • Niemann, J.; Porrmann, M.; Rückert, U.:
    A Scalable Parallel SoC Architecture for Network Processors.

    In: IEEE Computer Society Annual Symposium on VLSI 2005 (ISVLSI 2005), IEEE Computer Society Press, pp. 311-313, May 11-12, 2005.
  • Niemann, J.; Porrmann, M.; Sauer, C.; Rückert, U.:
    An Evaluation of the Scalable GigaNetIC Architecture for Access Networks.
    In: Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the ISCA 2005, on CD, Madison, Wisconsin, USA, June 4-8, 2005.
  • Paiz, C.; Kettelhoit, B.; Klassen, A.; Porrmann, M.; Rückert, U.:
    Dynamically Reconfigurable Hardware for Digital Controllers in Mechatronic Systems.

    In: IEEE International Conference on Mechatronics (ICM2005), pp. 675-680, Taipei, Taiwan, July 2005.
  • Eickhoff, R.; Niemann, J.; Porrmann, M.; Rückert, U.:
    Adaptable Switch boxes as on-chip routing nodes for networks-on-chip.

    In: From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), A. Rettberg , M. C. Zanella and F. J. Rammig Ed., pp. 201-210, Manaus, Brazil, August 15-17, 2005.
  • Griese, B.; Oberthür, S.; Porrmann, M.:
    Component case study of a self-optimizing RCOS/RTOS system: A reconfigurable network service.

    In: From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), A. Rettberg , M. C. Zanella and F. J. Rammig Ed., pp. 267-277, Manaos, Brazil, August 15-17, 2005.
  • Kalte, H.; Porrmann, M.:
    Context Saving and Restoring for Multitasking in Reconfigurable Systems.

    In: 15th International Conference on Field Programmable Logic and Applications, pp. 223-228, Tampere, Finland, 24-28 August 2005.
  • Köster, M.; Kalte, H.; Porrmann, M.:
    Run-Time Defragmentation for Partially Reconfigurable Systems.

    In: Proceedings of the International Conference on Very Large Scale Integration of System-on-Chip (IFIP VLSI-SoC), pp. 109-115, Perth, Australia, October 17-19, 2005.
  • Liß, C.; Peveling, R.; Porrmann, M.; Rückert, U.:
    Technologieplanung in der Mikroelektronik – von Moore’s Law zur Nanotechnologie-Roadmap.
    In: Symposium für Vorausschau und Technologieplanung, pp. 87-103, Berlin, Germany, Nov. 9-10, 2005.
  • Köster, M.; Kalte, H.; Porrmann, M.:
    Task Placement for Heterogeneous Reconfigurable Architectures.
    In: Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT'05), pp. 43-50, Singapore, December 11-14, 2005.
2004
  • Grünewald, M.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
    A framework for design space exploration of resource efficient network processing on multiprocessor SoCs.
    In: Proceedings of the 3rd Workshop on Network Processors & Applications, pp. 87-101, Madrid, Spain, February 14-15, 2004.
  • Grünewald, M.; Niemann, J.-C.; Porrmann, M.; Rückert, U.:
    A mapping strategy for resource-efficient network processing on multiprocessor SoCs.
    In: Proceedings of DATE: Design, Automation and Test in Europe, CNIT La Défense, pp. 758-763, Paris, France, February 16-20, 2004.
  • Kalte, H.; Porrmann, M.; Rückert, U.:
    Leistungsbewertung unterschiedlicher Einbettungsvarianten dynamisch rekonfigurierbarer Hardware.
    In: Workshop Proceedings: ARCS 2004 - Organic and Pervasive Computing, GI-Edition Lecture Notes in Informatics (LNI, pp. 235-244), Augsburg, March 26, 2004.
  • Kalte, H.; Porrmann, M.; Rückert, U.:
    System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement.
    In: 11th Reconfigurable Architectures Workshop (RAW 2004), on CD, Santa Fé, New Mexico, USA, April 26-27, 2004.
  • Kalte, H.; Köster, M; Kettelhoit, B; Porrmann, M; Rückert, U:
    A Comparative Study on System Approaches for Partially Reconfigurable Architectures.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ’04), pp. 70-76, Las Vegas, Nevada, USA, June 21-24, 2004.
  • Griese, B.; Vonnahme, E.; Porrmann, M.; Rückert, U.:
    Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.
    In: Proceedings of the 14th International Conference on Field Programmable Logic and its Applications (FPL2004), pp. 842-846, Antwerp, Belgium, 30 August  – 1 September 2004.
  • Franzmeier, M.; Pohl, C.; Porrmann, M.; Rückert, U.:
    Hardware Accelerated Data Analysis.
    In: Proceedings for the 4th International Conference on Parallel Computing in Electrical Engineering (PARALEC 2004), pp. 309-314, Dresden, Germany, September 7-10, 2004.
  • Grünewald, M.; Kastens, U.; Le, D. K.; Niemann, J.-C.; Porrmann, M.; Rückert, U.; Thies, Michael; Slowik, Adrian:
    Network Application Driven Instruction Set Extensions for Embedded Processing Clusters.
    In: Proceedings of PARELEC 2004, International Conference on Parallel Computing in Electrical Engineering, pp. 209-214, Dresden, Germany, September 7-10, 2004.
  • Vonnahme, E.; Griese, B.; Porrmann, M.; Rückert, U.:
    Dynamic reconfiguration of real-time network interfaces.
    In: Proceedings of the 4th International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), pp. 376-379, Dresden, Germany, September 7-10, 2004.
  • Vonnahme, E.; Griese, B.; Porrmann, M.; Rückert, U.:
    Dynamische Rekonfiguration echtzeitfähiger Netzwerkschnittstellen.
    In: Proceedings VDE Kongress 2004 - ITG Fachtagung „Ambient Intelligence“, VDE Verlag, Band 1, pp. 99-104, Berlin, Germany, October 18-20, 2004.
  • Niemann, J.-C.; Porrmann, M.; Rückert, U.:
    Parallele Architekturen für Netzwerkprozessoren.
    In: Proceedings  VDE Kongress 2004 – ITG Fachtagung Ambient Intelligence, VDE Verlag, Berlin, Volume 1, pp. 105-110, October 18-20 2004.
  • Pohl, C.; Franzmeier, M.; Porrmann, M.; Rückert, U.:
    gNBX – Reconfigurable Hardware Acceleration of Self-Organizing Maps.
    In: Proc. of the IEEE International Conference on Field Programmable Technology (FPT'04). Brisbane, Australia, pp. 97 – 104, December 6-8, 2004.
  • Kalte, H.; Porrmann, M.; Rückert, U.:
    Study on Column Wise Design Compaction for Reconfigurable Systems.
    In: Proc. of the IEEE International Conference on Field Programmable Technology (FPT'04). Brisbane, Australia, pp. 413 – 416, December 6-8, 2004.
  • Hagen, G.; Niemann, J.-C.; Porrmann, M.; Sauer, C.; Slowik, A.; Thies, M.:
    Developing an IP-DSLAM Benchmark for Network Processor Units.
    In: ANCHOR 2004, Advanced Networking and Communications Hardware Workshop, held in conjunction with the 31st Annual International Symposium on Computer Architecture (ISCA 2004), Munich, Germany, 2004.
2003
  • Bonorden, Olaf; Brüls, Nikolaus; Le, Dinh Khoi; Kastens, U.; Meyer auf der Heide, Friedhelm; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich; Slowik, Adrian; Thies, Michael:
    A holistic methodology for network processor design.
    In: Proceedings of the Workshop on High-Speed Local Networks held in conjunction with the 28th Annual IEEE Conference on Local Computer Networks (LCN2003), pp. 583-592, 20. - 24. Okt., 2003
2002
  • Brinkmann, André; Niemann, Jörg-Christian; Hehemann, Ingo; Langen, Dominik; Porrmann, Mario; Rückert, Ulrich:
    On-Chip Interconnects for Next Generation System-on-Chips.
    In: Proc. of the 15th Annual IEEE International ASIC/SOC Conference, pp. 212-215, Rochester, NY, USA, 25. - 28. Sep., 2002
  • Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs.
    In: Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002
  • Langen, Dominik; Niemann, Jörg-Christian; Porrmann, Mario; Kalte, Heiko; Rückert, Ulrich:
    Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation.
    In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002
  • Porrmann, Mario; Franzmeier, Marc; Kalte, Heiko; Witkowski, Ulf; Rückert, Ulrich:
    A reconfigurable SOM hardware accelerator.
    In: Proceedings of the 10th European Symposium on Artificial Neural Networks, ESANN'2002, pp. 337-342, Bruges, Belgium, Apr., 2002
  • Porrmann, Mario; Witkowski, Ulf; Kalte, Heiko; Rückert, Ulrich:
    Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations.
    In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2002), pp. 1048-1057, Montpellier, France, 2002
  • Porrmann, Mario; Witkowski, Ulf; Kalte, Heiko; Rückert, Ulrich:
    Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator.
    In: Proceedings of the 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (PDP 2002), pp. 243-250, Gran Canaria Island, Spain, Jan., 2002
2001
  • Niemann, Jörg-Christian; Witkowski, Ulf; Porrmann, Mario; Rückert, Ulrich:
    Extension Module for Application-Specific Hardware on the Minirobot Khepera.
    In: Autonomous Minirobots for Research and Edutainment (AMiRE 2001), pp. 279-288, Paderborn, Germany, 22. - 24. Okt., 2001
  • Porrmann, Mario; Rückert, Ulrich; Landmann, Jörg; Marks, Karl Michael:
    XipChip - A Multiprocessor CPU for Multifunction Peripherals.
    In: Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), Band 15, pp. 512-517, Orlando, Florida, USA, Jul., 2001
  • Porrmann, Mario; Rüping, Stefan; Rückert, Ulrich:
    The Impact of Communication on Hardware Accelerators for Neural Networks.
    In: Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), Band 3, pp. 248-253, Orlando, Florida, USA, Jul., 2001
  • Porrmann, Mario; Kalte, Heiko; Witkowski, Ulf; Niemann, Jörg-Christian; Rückert, Ulrich:
    A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature Maps.
    In: Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), 2001, Band 3, pp. 242-247, Orlando, Florida, USA, Jul., 2001
2000
  • Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics.
    In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA´2000), Band 5, pp. 2819-2824, Monte Carlo Resort, Las Vegas, Nevada, USA, 2000
  • Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    Rapid Prototyping System für dynamisch rekonfigurierbare Hardwarestrukturen.
    In: Workshop: Architekturentwurf und Entwicklung eingebetteter Systeme (AES2000), pp. 149-157, Karlsruhe, Germany, 2000
1999
  • Porrmann, Mario; Rüping, Stefan; Rückert, Ulrich:
    SOM Hardware with Acceleration Module for Graphical Representation of the Learning Process.
    In: Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems (MicroNeuro99), pp. 380-386, Granada, Spain, 7. - 9. Apr., 1999
1998
  • Porrmann, Mario; Heittmann, Arne; Rüping, Stefan; Rückert, Ulrich:
    A Hybrid Knowledge Processing System.
    In: Proceedings of the Conference Neural Networks and their Applications (NEURAP), pp. 177 - 184, Marseille, France, 11. - 13. Mrz., 1998
1997
  • Porrmann, Mario; Landmann, Jörg; Marks, Karl Michael; Rückert, Ulrich:
    HIBRIC-MEM, a Memory Controller for PowerPC Based Systems.
    In: Proceedings of the 23rd EUROMICRO Conference, pp. 653-663, Budapest, Ungarn, 1. - 4. Sep., 1997
  • Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich:
    SOM Hardware-Accelerator.
    In: Workshop on Self-Organizing Maps (WSOM), Nr.1997, pp. 136-141, Espoo, Finnland, 4. - 6. Jun., 1997
  • Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich:
    A High Performance SOFM Hardware-System.
    In: Proceedings of the International Work-Conference on Artificial and Natural Neural Networks (IWANN´97), pp. 772-781, Lanzarote, Spain, 4. - 6. Jun., 1997
1996
  • Palm, Günther; Rückert, Ulrich; Porrmann, Mario; Schwenker, Friedhelm:
    Neuronale Assoziativspeicher.
    In: Neuroinformatik Statusseminar, pp. 419-432, Apr., 1996

Weitere Publikationen und eingeladene Vorträge (Auswahl)

  • Braun, L. D.; Porrmann, M.:
    The Comprehensive MAC Taxonomy Database: comatose.
    Technical Report, 2018, DOI: doi:10.4119/unibi/2918509
  • Kaiser, M.; Pilz, S.; Porrmann, F.; Hagemeyer, J.; Porrmann, M.:
    Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs.
    In: 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book. Vol 12, pp. 48-49, Bielefeld; 2018.
  • Kaiser, M.; Griessl, R.; Hagemeyer, J.; Jungewelter, D.; Porrmann, F.; Pilz, S.; Porrmann, M.; vor dem Berge, M.; Krupop, S.:
    A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing.
    In: Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘17), held in conjunction with Supercomputig 2017, Denver, CO, USA, November 17, 2017.
  • Porrmann, M.:
    M2DC – Modular Microserver Data Centre.

    ARM Research Summit 2017 Cambridge, UK, September 11-13, 2017 (Invited Talk).
  • Porrmann, M.:
    Neuromorphic computing – Disruptive technology for automotive applications?

    Embedded Multi-Core Conference (EMCC 2017), Munich, Germany, June 20-22, 2017 (Keynote Talk).
  • Griessl, R.; Hagemeyer, J.; Porrmann, M.; et al.:
    M2DC – Modular Microserver Data Centre.

    Poster presentation at ISC High Performance, Frankfurt, Germany, June 18-22, 2017.
  • Romoth, J.; Porrmann, M.; Rueckert, U.:
    Survey of FPGA applications in the period 2000 – 2015.
    Technical Report, March 2017, DOI: 10.13140/RG.2.2.16364.56960
  • Griessl, R.; Peykanu, M.; Tigges, L.; Hagemeyer, J.; Porrmann, M.:
    FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers.
    In: Reconfigurable Computing – From Embedded Systems to Reconfigurable Hyperscale Servers. Workshop at the 26th International Conference on Field-Programmable Logic and Applications FPL 2016, 2nd September 2016, Lausanne, Switzerland.
  • Cozzi, D.; Jungewelter, D.; Korf, S.; Hagemeyer, J.; Porrmann, M.:
    Dynamically Reconfigurable Hardware for Resource Efficiency and Fault Tolerance in Space Applications.
    In: SEFUW 2014 – Space FPGA Users Workshop, 2nd Edition, ESA/ESTEC, Noordwijk, The Netherlands, September 16-18, 2014.
  • Korf, S.; Cozzi, D.; Jungewelter, D.; Hagemeyer, J.; Porrmann, M.; Ilstad, J.:
    Leveraging dynamic reconfiguration to increase fault-tolerance in FPGA-based satellite systems.
    In: Design, Automation and Test in Europe – DATE 2014, University Booth, Dresden, Germany, March 24-27, 2014.
  • Porrmann, M.:
    Dynamically Reconfigurable Hardware for Satellite Payload Processing.
    5th tubs.CITY Symposium – Managing change and autonomy for critical applications, Braunschweig, Germany, October 30-31, 2013 (Invited Talk).
  • Porrmann, M.:
    Dynamically Reconfigurable Hardware for Satellite Payload Processing.
    In: Military and Aerospace Programmable Logic Devices (MAPLD 2013), San Diego, CA, USA, April 9-12, 2013.
  • Cassano, L.; Cozzi, D.; Korf, S.; Hagemeyer, J.; Porrmann, M.; Sterpone, L.:
    A CAD Flow for On-Line Testing and Patching Permanent Radiation Effects in Reconfigurable Systems.
    In: Military and Aerospace Programmable Logic Devices (MAPLD 2013), San Diego, CA, USA, April 9-12, 2013.
  • Porrmann, M.:
    Entwicklung intelligenter technischer Systeme – Ressourceneffiziente Schaltungstechnik.
    Vortrag im Rahmen der Veranstaltung „Wie wird mein Produkt intelligent?“, Salzkotten, Germany, November 16, 2012 (Invited Talk).
  • Porrmann, M.:
    Dynamically Reconfigurable Systems: Evolution, Applications, and Perspectives.
    In: ACCS 2012 – ACCS Workshop on Adaptive Computing, Bangalore, India, September 14, 2012 (Invited Talk).
  • Porrmann, M.:
    Dynamically Reconfigurable Systems: Evolution, Applications, and Perspectives.
    In: Conference on Design & Architectures for Signal & Image Processing, DASIP 2011, Tampere, Finland, November 2-4, 2011 (Keynote Talk).
  • Romoth, J.; Hagemeyer, J.; Porrmann, M.; Rueckert, U.:
    Fast Design-space Exploration with FPGA Clusters.
    In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing (DATE 2011), Grenoble, France, March 18, 2011.
  • Koester, M.; Hagemeyer, J.; Margaglia, F.; Porrmann, M.; Dittmann, F.; Ditze, M.; Sterpone, L.; Harris, J.; Ilstad, J.:
    Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications.

    In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing (DATE 2011), Grenoble, France, March 18, 2011.
  • Griessl, R.; Herbrechtsmeier, S.; Porrmann, M.; Rueckert, U.:
    A Low-Power Vision Processing Platform for Mobile Robots.
    In: Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures, September 4, 2011, Chania, Crete, Greece.
  • Pohl, C.; Fuest, R.; Porrmann, M.; Rückert, U.:
    vMAGIC - Automatic Code Generation for VHDL.
    In: newsletter edacentrum, pp. 7-10, Jul. 2010
  • Jungeblut, T.; Lütkemeier S.; Siever, G.; Porrmann, M.; Rückert, U.:
    A Modular Design Flow for Very Large Design Space Explorations.
    In: Proceedings of CDNLive! EMEA 2010, Munich, Germany, May 4-6, 2010.
  • Grassi, P. R.; Pohl, C.; Porrmann, M.:
    Reconfiguration Viewer.
    In. Design, Automation and Test in Europe DATE, University Booth, Nice, France, April 20-24, 2009.
  • Pohl, C.; Fuest, R.; Porrmann, M.:
    Manageable Dynamic Reconfiguration with EVE – Extendable VHDL Editor.
    In: Design, Automation and Test in Europe DATE, University Booth, Nice, France, April 20-24, 2009.
  • Liß, C.; Porrmann, M.; Rückert, U.:
    InCyte ChipEstimator in Research and Education.
    In: CDNLive, EMEA2009, Munich, Germany, May 18-20, 2009.
  • Pohl, C.; Paiz, C.; Porrmann, M.:
    A Hardware-in-the-Loop Design Environment for FPGAs.
    In: Design, Automation and Test in Europe DATE, University Booth, Munich, Germany, March 10-14, 2008.
  • Jungeblut, T.; Dreesen, R.; Porrmann, M.; Rückert, U.; Hachmann, U.:
    Design Space Exploration for Resource Efficient VLIW-processors.
    In: Design, Automation and Test in Europe DATE, University Booth, Munich, Germany, March 10-14, 2008.
  • Hagemeyer, J.; Kettelhoit, B.; Koester, M.; Porrmann, M.:
    INDRA – Integrated Design Flow for Reconfigurable Architectures.
    In: Design, Automation and Test in Europe DATE, University Booth, on CD, Nice, France, April 16-20, 2007.
  • Jungeblut, T.; Grünewald, M.; Porrmann, M.; Rückert, U.:
    Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks.
    In: Design, Automation and Test in Europe DATE, University Booth, on CD, Nice, France, April 16-20, 2007.
  • Porrmann, M.:
    A Layer-Model Based Methodology for the Design of Dynamically Reconfigurable Systems.
    In: 2nd International Conference on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, Peradeniya, Sri Lanka, August, 8-11, 2007 (Invited Talk).
  • Porrmann, M.:
    Flexible Hardware Platforms for Dynamic Reconfiguration.
    In: 2nd International Conference on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, Peradeniya, Sri Lanka, August, 8-11, 2007 (Invited Talk).